Design and Simulation of Adiabatic Architectures

This DC will start surveying the state-of-the-art RC architectures, their instruction sets, and their main implementations. The DC will then first work on developing a software simulation platform for reversible architectures. He/she will follow the concept of chiplets, with an energy-efficient chiplet dedicated to traditional processing (e.g. Arm-based processing cores). These cores would provide I/O, bootup, configuration and, if needed, would be Linux capable. A second chiplet would be dedicated to general purpose computing using RC adiabatic architectures. The simulation and novel reversible architectures on the second chiplet would be the main research topic. Additionally, the DC will investigate the interaction between standard processors and RC architectures.

1) Simulation platform for general purpose architecture based on RC; 2) Energy simulation platform for general purpose RC architecture; 3) Novel insights in combining standard processing cores with new RC architectures.

M14, UCPH, R. Glück, requirements from compilation; M25, SDU, U. P. Schultz, simulation of drones architectures.